This disclosure relates to comparators, memory region detection, and methods. Comparator circuitry may be used to detect whether a value under test is above or below a threshold. An example of the use of such circuitry is found in memory region detection circuitry. This can be used, for example, in situations where it is desired to know whether a memory address is above or below a threshold address, or (if two separate thresholds are used) if it is within a memory region defined by upper and lower limit addresses.
For example, one or more attributes (such as programmable attributes) can be associated with memory regions, so that a detection of whether a memory address falls within that region can be used to control memory access to that address in dependence upon those one or more attributes. An example of such an attribute is an attribute indicating whether write operations can be performed to that memory region. Another example is whether the requesting entity (for example, an application or a virtual machine) has permission to access that memory region at all.
Some previously proposed arrangements use so-called bit masking in which a subset of address bits are compared with predetermined values, so that an address is detected to lie in a memory region if the subset of bits matches the mask. However, this requires the memory regions to be aligned with boundaries represented by particular address bits, and allows only limited flexibility in the size and alignment of the memory regions. To implement a single arbitrary memory region using bit masks can require a significant number of individual masks. Therefore, in other arrangements, an arithmetic comparison is used. Here, a memory address under test is compared by arithmetic comparison with upper and lower limit addresses to detect whether the address under test lies in a memory region defined by the upper and lower limit addresses. However, this arithmetic comparison can result in the address comparison, which can be on a critical path for memory and processor performance, imposing a delay corresponding to the time taken to perform the comparisons.